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YMF740C
DS-1L
OVERVIEW
YMF740C (DS-1L) is a high performance audio controller for the PCI Bus. DS-1L consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 41 concurrent audio streams with the Bus Master DMA engine. The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio provides 32-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware accelerator, Downloadable Sound (DLS) and DirectMusic accelerator. Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver. To achieve legacy DMAC compatibility on the PCI, DS-1L supports PC/PCI protocols. DS-1L supports the connection to AC'97 which provides high quality DAC, ADC and analog mixing.
FEATURES
* PCI 2.1 Compliant * PC'97/PC'98 specification Compliant * PCI Bus Power Management rev. 1.0 Compliant (Support D0, D2 and D3 state) * PCI Bus Master for PCI Audio True Full Duplex Playback and Capture with different Sampling Rate Maximum 32-voice XG capital Wavetable Synthesizer including GM compatibility DirectSound Hardware Acceleration DirectMusic Hardware Acceleration Downloadable Sound (DLS) level-1 * Supports PC/PCI DMA for legacy DMAC (8237) emulation * Legacy Audio compatibility FM Synthesizer Hardware Sound Blaster Pro compatibility MPU401 UART mode MIDI interface Joystick * Supports AC'97 Interface (AC-Link) * Hardware Volume Control * Single Crystal operation (24.576MHz) * 5V Power supply for I/O. 3.3V Power supply for Internal core logic * 144-pin LQFP (YMF740C-V)
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation.
YAMAHA CORPORATION
YMF740C CATALOG CATALOG No.:LSI-4MF740C20 September1999 1998 January 14, 21,
YMF740C-V
YMF740C
PIN CONFIGURATION
GP4 GP5 GP6 GP7 RXD TXD VOLDW# VOLUP# VDD5 VDD3 VSS VSS IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 INTA# VSS RST# VDD5 PVSS PCICLK PVDD GNT# REQ# AD31 AD30 AD29 PVSS AD28 AD27 AD26 PVSS AD25 AD24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 Pin LQFP Top View
-2-
CBE3# PVDD PVSS IDSEL AD23 AD22 AD21 PVSS AD20 AD19 PVSS AD18 AD17 AD16 PVDD PVSS VSS VDD3 CBE2# FRAME# IRDY# TRDY# PVSS DEVSEL# STOP# PERR# SERR# PVSS PAR CBE1# AD15 PVSS PVDD AD14 AD13 PVSS GREF GP3 GP2 GP1 GP0 TEST2# TEST1# TEST0# NC LVSS LOOPF1 LOOPF0 LVDD NC TEST4# VDD5 XO24 XI24 VSS VSS VDD3 NC TEST7# TEST6# TEST5# CMCLK CSDO CBCLK CSDI CSYNC CRST# TEST3# NC NC NC NC 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC NC NC NC NC NC NC NC VSS VSS VDD3 VDD5 PVDD NC PCREQ# PCGNT# NC AD0 AD1 PVSS AD2 AD3 AD4 PVSS AD5 AD6 AD7 PVSS PVDD CBE0# AD8 AD9 PVSS AD10 AD11 AD12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
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YMF740C
PIN DESCRIPTION 1. PCI Bus Interface (52-pin)
name PCICLK RST# AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQA# GNTA# PCREQ# PCGNT# PERR# SERR# INTA# I/O I I IO IO IO IO IO IO IO I IO O I O I IO O O Type P P Ptr Ptr Ptr Pstr Pstr Pstr Pstr P Pstr P P Ptr Ptr Pstr Pod Pod Size PCI Clock Reset Address / Data Command / Byte Enable Parity Frame Initiator Ready Target Ready Stop ID Select Device Select PCI Request PCI Grant PC/PCI Request PC/PCI Grant Parity Error System Error Interrupt signal output for PCI bus function
2. Legacy Device Interface (16-pin)
name IRQ5 I/O O type Ttr size 12mA function Interrupt5 of Legacy Audio It is directly connected to the interrupt signal of System I/O chip. IRQ7 IRQ9 IRQ10 IRQ11 GP[3:0] GP[7:4] GREF RXD TXD O O O O I I I I O Ttr Ttr Ttr Ttr A Tup A Tup T 12mA 12mA 12mA 12mA 3mA Interrupt7 of Legacy Audio Interrupt9 of Legacy Audio Interrupt10 of Legacy Audio Interrupt11 of Legacy Audio. Game Port Game Port Reference for Game Port MIDI Data Receive MIDI Data Transfer
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YMF740C
3. AC'97 Interface (6-pin)
name CRST# CMCLK CBCLK CSDO CSDI CSYNC I/O O O I O I O Type T C T T T T Size 6mA 6mA 6mA function Reset signal for AC'97 Master Clock of AC link (24.576MHz) and AC-link: Bit Clock for AC'97 audio data AC-link: AC`97 Serial audio output data AC-link: AC'97 Serial audio input data AC-link: Synchronized signal
4. Miscellaneous (14-pin)
name VOLUP# VOLDW# XI24 XO24 TEST[7:4,2:0]# TEST3# LOOPF[1:0] I/O I I I O I IO type Tup Tup C C Tup Tup size 2mA 3mA function Hardware Volume (Up) Hardware Volume (Down) 24.576 MHz Crystal 24.576 MHz Crystal Test pins (Do not connect externally) Test pin (Connect to ground) Capacitor of PLL
5. Power Supply (39-pin)
name PVDD[5:0] PVSS[14:0] LVDD LVSS VDD3[3:0] VDD5[3:0] VSS[7:0] I/O type size function Power supply for PCI Bus Interface (+5.0) Ground for PCI Bus Interface Power supply for PLL Filter (+3.3) Ground for PLL Filter Power supply (+3.3V) Power supply (+5.0V) Ground
TYPE
T : TTL Ttr : Tri-State TTL Tup : Pull up (Max. 300kohm) TTL A : Analog C : CMOS P : PCI Ptr : Tri-State PCI Pstr : Sustained Tri-Sate PCI Pod : Open Drain PCI
Note) All pins except the above pins are NC (No Connection) pins.
Do not connect externally.
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YMF740C
BLOCK DIAGRAM
PC-PCI
Legacy Audio SB Pro FM MPU401 Joystick Rate Converter / Mixer
AC'97 PCI Bus Interface BUS Master DMA Controller XG Synthesizer Direct Sound Acc. Wave In/Out Memory PCI Audio Interface
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YMF740C
DOS VM MMSystem
DLS Appllication Win16API WaveOut Device MidiOut Device DRV for PCI Audio Win32API
SYSTEM DIAGRAM
DirectX Application
MidiOut Device DRV for Legacy
MidiIn Device
WaveIn Device
Msjstck.drv XG/DLS Engine DirectSound HAL DirectSound VxD
I/O Traps
I/O Traps
-6DS-1L Slot Manager (Up to 32-sound) VxD for Legacy Soft Effect VxD for PCI Audio MPU401 PCI Audio
Vjoyd.vxd
Joystick
FM
SB Pro
YMF740C(DS-1L)
January 14, 1999
YMF740C
FUNCTION OVERVIEW 1. PCI INTERFACE
DS-1L supports the PCI bus interface and complies to PCI revision 2.1.
1-1. PCI Bus Command
DS-1L supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0]# 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command Interrupt Acknowledge (not support) Special Cycle (not support) I/O Read I/O Write reserved reserved Memory Read Memory Write reserved reserved Configuration Read Configuration Write Memory Read Multiple (not support) Dual Address Cycle (not support) Memory Read Line (not support) Memory Write and Invalidate (not support)
DS-1L does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or reserved.
1-1-2. Master Device Mode C/BE[3:0]# 0 0 1 1 1 1 0 1 Command Memory Read Memory Write
When DS-1L becomes a Master Device, it generates only memory write and read cycle commands.
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YMF740C
1-2. PCI Configuration Register
In addition to the Configuration Register defined by PCI Revision 2.1, DS-1L provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register.
Offset 00-03h 04-07h 08-0Bh 0C-0Fh 10-13h 14-2Bh 2C-2Fh 30-33h 34-37h 38-3Bh 3C-3Fh 40-43h 44-47h 48-4Bh 4C-4Fh 50-53h 54-57h 58-5Bh 5C-FFh
b[31..24] Device ID Status Base Class Code Reserved
b[23..16]
b[15..8] Vendor ID Command Programming IF Latency Timer
b[7..0]
Sub Class Code Header Type
Revision ID Reserved
PCI Audio Memory Base Address Reserved Subsystem ID Reserved Reserved Reserved Maximum Latency Minimum Grant Interrupt Pin Interrupt Line Cap Pointer Subsystem Vendor ID
Extended Legacy Audio Control Subsystem ID Write DS-1L Power Control Reserved Power Management Capabilities Reserved Reserved Reserved
Legacy Audio Control Subsystem Vendor ID Write DS-1L Control Reserved Next Item Pointer Capability ID
Power Management Control / Status ACPI Mode
Reserved
registers are hardwired to "0".
All data written to these registers are discarded.
The values
read from these registers are all zero.
DS-1L can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.
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YMF740C
00 - 01h: Vendor ID
Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID
b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. 1073h. This register is hardwired to
02 - 03h: Device ID
Read Only Default: 000Ch Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Device ID
b[15:0] ........Device ID This register contains the Device ID of DS-1L. This register is hardwired to 000Ch.
04 - 05h: Command
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 SER b7 b6 PER b5 b4 b3 b2 BME b1 MS b0 -
b1................MS: Memory Space This bit enables DS-1L to response to Memory Space Access. "0": DS-1L ignores Memory Space Access. "1": DS-1L responds to Memory Space Access. b2................BME: Bus Master Enable This bit enables DS-1L to act as a master device on the PCI bus. "0": Do not set DS-1L to be the master device. "1": Set DS-1L to be the master device. b6................PER: Parity Error Response This bit enables DS-1L responses to Parity Error. "0": DS-1L ignores all parity errors. "1": DS-1L performs error operation when DS-1L detects a parity error. (default) (default)
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YMF740C
b8................SER: SERR# Enable This bit enables DS-1L to drive SERR#. "0": Do not drive SERR#. Error on special cycle. (default) "1": Drives SERR# when DS-1L detects an Address Parity Error on normal target cycle or a Data Parity
06 - 07h: Status
Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit
b15 DPE b14 SSE b13 RMA b12 RTA b11 STA b10 b9 b8 DPD b7 b6 b5 b4 CAP b3 b2 b1 b0 DEVT
b4................CAP: Capability
(Read Only) This bit is read only. When 58-59h :
This bit indicates that DS-1L supports the capability register.
ACPI Mode register, ACPI bit is "0", the bit is "1". When ACPI bit is "1", the bit is "0". b8................DPD: Data Parity Error Detected This bit indicates that DS-1L detects a Data Parity Error during a PCI master cycle. b[10:9] ........DEVT: DEVSEL Timing This bit indicates that the decoding speed of DS-1L is Medium. b11..............STA: Signaled Target Abort This bit indicates that DS-1L terminates a transaction with Target Abort during a target cycle. b12..............RTA: Received Target Abort This bit indicates that a transaction is terminated with Target Abort while DS-1L is in the master memory cycle. b13..............RMA: Received Master Abort This bit indicates that a transaction is terminated with Master Abort while DS-1L is in the master memory cycle. b14..............SSE: Signaled System Error This bit indicates that DS-1L asserts SERR#. b15..............DPE: Detected Parity Error This bit indicates that DS-1L detects Address Parity Error or Data Parity Error during a transaction.
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YMF740C
08h: Revision ID
Read Only Default: 03h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Revision ID
b[7:0] ..........Revision ID This register contains the revision number of DS-1L. This register is hardwired to 03h.
09h: Programming Interface
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Programming Interface
b[7:0] ..........Programming Interface This register indicates the programming interface of DS-1L. This register is hardwired to 00h.
0Ah: Sub-class Code
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Sub-class Code
b[7:0] ..........Sub-class Code This register indicates the sub-class of DS-1L. Audio Sub-class. This register is hardwired to 01h. DS-1L belongs to the
0Bh: Base Class Code
Read Only Default: 04h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Base Class Code
b[7:0] ..........Base Class Code This register indicates the base class of DS-1L. the Multimedia Base Class. This register is hardwired to 04h. DS-1L belongs to
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YMF740C
0Dh: Latency Timer
Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Latency Timer
b[7:0] ..........Latency Timer When DS-1L becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer.
0Eh: Header Type
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Header Type
b[7:0] ..........Header Type This register indicates the device type of DS-1L. This is hardwired to 00h.
10 - 13h: PCI Audio Memory Base Address
Read / Write Default: 00000000h Access Bus Width: 8, 16, 32-bit
b15
MBA
b14 b30
b13 b29
b12 b28
b11 b27
b10 b26
b9 b25
b8 b24
b7 b23
b6 b22
b5 b21
b4 b20
b3 b19
b2 b18
b1 b17
b0 b16
b31
MBA (higher)
b[31:15] ......MBA: Memory Base Address This register indicates the physical Memory Base address of the PCI Audio registers in DS-1L. address can be located anywhere in the 32-bit address space. prefetchable. DS-1L needs 32768-bytes of memory address space. The base
Data in the DS-1L register is not
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YMF740C
2C-2Dh: Subsystem Vendor ID
Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID
b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or This register is read only. To
systems made by different IHVs using the same chip by the same vendor.
write the IHV's Vendor ID, use 44-45h (Subsystem Vendor ID Write Register). The default value is the YAMAHA's Vendor ID, 1073h. IHVs must change this ID to their Vendor ID in the BIOS POST routine.
2E-2Fh: Subsystem ID
Read Only Default: 000Ch Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID
b[15:0] ........Subsystem ID This register contains the Subsystem ID. In general, this ID is used to distinguish adapters or systems This register is read only. To write
made by different IHVs using the same chip by the same vendor. the IHV's Device ID, use 46-47h (Subsystem ID Write Register). The default value is the YAMAHA's Device ID, 000Ch. BIOS POST routine.
IHVs must change this ID to their ID in the
34h: Capability Register Pointer
Read Only Default: 50h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Capability Register Pointer
b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is "0". registers as the capabilities. Configuration register, and this register indicates "50h". When ACPI bit is "1", this register indicates "00h". DS-1L provides PCI Bus Power Management The Power Management registers are mapped to 50h - 57h in the PCI
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YMF740C
3Ch: Interrupt Line
Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Line
b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to.
3Dh: Interrupt Pin
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Pin
b[7:0] ..........Interrupt Pin DS-1L supports INTA# only. This register is hardwired to 01h.
3Eh: Minimum Grant
Read Only Default: 05h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Minimum Grant
b[7:0] ..........Minimum Grant This register indicates the length of the burst period required by DS-1L. This register is hardwired to 05h.
3Fh: Maximum Latency
Read Only Default: 19h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Maximum Latency
b[7:0] ..........Maximum Latency This register indicates how often DS-1L generates the Bus Master Request. This register is hardwired to 19h.
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YMF740C
40 - 41h: Legacy Audio Control
Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit
b15 LAD b14 "0" b13 b12 MPUIRQ b11 b10 b9 SBIRQ b8 b7 b6 b5 I/O b4 MIEN b3 b2 b1 b0 SDMA MEN GPEN FMEN SBEN
b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to "0". The FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to "0". "0": Disable the mapping of the SB block to the I/O space "1": Enable the mapping of the SB block to the I/O space b1................FMEN: FM Synthesizer Enable This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits, when LAD is set to "0". FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to "0". "0": Disable the mapping of the FM Synthesizer block to the FMIO space "1": Enable the mapping of the FM Synthesizer block to the FMIO space (default) After setting FMEN to "1", about 100 msec is necessary before accessing these I/O space. b2................GPEN: Gameport Enable This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD is set to "0". "0": Disable the mapping of the Joystick block "1": Enable the mapping of the Joystick block b3................MEN: MPU401 Enable This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when LAD is set to "0". "0": Disable the mapping of the MPU401 block "1": Enable the mapping of the MPU401 block b4................MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to "0" and MEN is set to "1". MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. "0": The MPU401 block can not use the interrupt service. "1": The MPU401 block can use interrupt signals determined by the MPUIRQ bits. b5................I/O: I/O Address Aliasing Control This bit selects the number of bits to decode for the I/O address of each block. "0": 16-bit address decode "1": 10-bit address decode (default) (default) (default) (default) (default)
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YMF740C
b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. "0": "1": "2": "3": DMA ch0 DMA ch1 reserved DMA ch3 (default)
b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. "0": "1": "2": "3": "4": "5" - "7": IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 reserved. (default)
b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select When MIEN is set to "1", these bits select the interrupt channel for the MPU401 block. "0": "1": "2": "3": "4": "5" - "7": IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 reserved (default)
Same interrupt channels can be assigned to SBIRQ and MPUIRQ. b14..............Reserved Bit Hardwire to "0". b15..............LAD: Legacy Audio Disable This bit disables the Legacy Audio block. "0": Enables the Legacy Audio block "1": Disables the Legacy Audio block the PCI bus. (default) When this bit is set to "1", DS-1L does not respond to the I/O Target transaction for legacy I/O address on
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YMF740C
42 - 43h: Extended Legacy Audio Control
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 IMOD b14 b13 b12 b11 b10 b9 b8 MAIM b7 JSIO b6 b5 b4 b3 b2 SBIO b1 b0 SBVER SMOD MPUIO FMIO
b[1:0] ..........FMIO: FM I/O Address allocation These bits determine the base I/O address for the of the FM Synthesizer block (FMBase). FM Synthesizer block uses 4 bytes in the I/O address space. "0": "1": "2": "3": 388h 398h 3A0h 3A8h (default)
b[3:2] ..........SBIO: SB I/O Address allocation These bits determine the base I/O address for the Sound Blaster Pro block (SBBase). bytes in the I/O address space. "0": "1": "2": "3": 220h 240h 260h 280h (default) This block uses 16
b[5:4] ..........MPUIO: MPU I/O Address allocation These bits determine the base I/O address for the MPU401 block (MPUBase). in the I/O address space. "0": "1": "2": "3": 330h 300h 332h 334h (default) This block uses 2 bytes
b[7:6] ..........JSIO: Joystick I/O Address allocation These bits determine the base I/O address for the Joystick block (JSBase). I/O address space. "0": "1": "2": "3": 201h 202h 204h 205h (default) This block uses 1 byte in the
b8................MAIM: MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing MPU401 mode form default to UART, is returned. "0": Interrupt is asserted when the acknowledge is returned. "1": Interrupt is masked when the acknowledge is returned. (default)
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YMF740C
b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. "0": "1" - "3": PC/PCI reserved (default)
b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. DSP command. "0": "1": "2": "3": ver 3.01 ver 2.01 ver 1.05 reserved (default) The value set in these bits is returned by sending the E1h
b15..............IMOD: Legacy IRQ mode DS-1L supports 2 types of interrupt protocols: PCI interrupt (INTA#) and Legacy interrupt (IRQs). interrupt protocol is selected by IMOD as follows. "0": "1": Legacy interrupt (IRQs) PCI interrupt (INTA#) SBIRQ and MPUIRQ. Only one protocol can be used at once. (default) The
The interrupt channels for IRQs are determined by
44-45h: Subsystem Vendor ID Write Register
Read / Write Default: 1073h Access Bus Width: 16-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID Write
b[15:0] ........Subsystem Vendor ID Write Register This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register). The default value is the YAMAHA Vendor ID, 1073h. the BIOS POST routine. IHVs must change this ID to their Vendor ID in
46-47h: Subsystem ID Write Register
Read / Write Default: 000Ch Access Bus Width: 16-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID Write
b[15:0] ........Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register). The default value is the DS-1L Device ID, 000Ch. POST routine. IHVs must change this ID to their ID in the BIOS
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YMF740C
48-49h: DS-1L Control Register
Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CRST
b0................CRST: AC'97 Software Reset Signal Control This bit controls the CRST# signal. "0": Inactive (CRST#=High) "1": Active (CRST#=Low) (default)
4A-4Bh: DS-1L Power Control Register
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 PR7 b14 PR6 b13 PR5 b12 PR4 b11 PR3 b10 PR2 b9 PR1 b8 PR0 b7 b6 b5 PSN b4 PSL1 b3 b2 b1 b0 PSL0 DPLL1 DPLL0 DMC
b0................DMC: Disable Master Clock Oscillation Setting this bit to "1" disables the oscillation of the Master Clock (24.576 MHz). "0": Normal "1": Disable b1................DPLL0: Disable PLL0 Clock Oscillation Setting this bit to "1" disables the oscillation of PLL for the Legacy Audio function. "0": Normal "1": Disable b2................DPLL1: Disable PLL1 Clock Oscillation Setting this bit to "1" disables the oscillation of PLL for the PCI Audio function. "0": Normal "1": Disable b3................PSL0: Power Save Legacy Audio Block 0 Setting this bit to "1" stops providing the clock with the Legacy Audio function block 0. includes FM Synthesizer and SB Pro engines. "0": Normal "1": Power Save b4................PSL1: Power Save Legacy Audio Block 1 Setting this bit to "1" stops providing the clock with the Legacy Audio function block 1. includes MPU401 and Joystick. "0": Normal "1": Power Save (default) This block (default) This block (default) (default) (default)
January 14, 1999 -19-
YMF740C
b5................PSN: Power Save PCI Audio block Setting this bit to "1" stops providing the clock with the PCI Audio function block. PCI Audio, SRC, AC'97 I/F and H/W Vol. "0": Normal "1": Power Save b8................PR0: AC'97 Power down Control 0 This bit controls the power state of the ADC and Input Mux in AC'97. "0": Normal "1": Power down b9................PR1: AC'97 Power down Control 1 This bit controls the power state of the DAC in AC'97. "0": Normal "1": Power down b10..............PR2: AC'97 Power down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in AC'97. the Reference Voltage of AC'97. "0": Normal "1": Power down b11..............PR3: AC'97 Power down Control 3 This bit controls the power state of the Analog Mixer (Vref off) in AC'97. Reference Voltage of AC'97. "0": Normal "1": Power down b12..............PR4: AC'97 Power down Control 4 This bit controls the power state of the AC-link in AC'97. "0": Normal "1": Power down b13..............PR5: AC'97 Power down Control 5 Setting this bit to "1" disables the internal clock of AC'97. master clock is supplied from DS-1L. both PR5 and PSN bits to "1". "0": Normal "1": Disable b[15:14] ......AC'97 Power down Control 6 and 7 These bits control PR6 and PR7 status of the power control register in AC'97. (default) In case AC'97 is used with DS-1L, the (default) (default) This power state removes (default) This power state retains (default) (default) (default) This block includes
Therefore, when the clock of AC'97 is stopped completely, set
January 14, 1999 -20-
YMF740C
PSL0 Legacy func. 0 Master (24.576MHz) PLL0 33.87MHz FM Synthesizer SB Pro PSL1
DMC
DPLL0
Legacy func. 1 MPU401 Joystick
PSN PCI func. 0 PLL1 49.152MHz AC'97 I/F H/W Vol. DPLL1 PCI Audio SRC
PCI func. 1 PCICLK (33MHz) PCI I/F PC/PCI
- Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to "1", when DMC bit is set to "1". - Set PSL0 and PSL1 bits to "1", when DPLL0 bit is set to "1". - Set PSN bit to "1", when DPLL1 bit is set to "1".
January 14, 1999 -21-
YMF740C
50h: Capability ID
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Capability ID
b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. hardwired to 01h. This register is
51h: Next Item Pointer
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Next Item Pointer
b[7:0] ..........Next Item Pointer DS-1L does not provide other new capability besides Power Management. 00h. This register is hardwired to
52-53h: Power Management Capabilities
Read Only Default: 0401h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 D2S b9 b8 b7 b6 b5 b4 b3 b2 b1 Version b0
b[2:0] ..........Version These bits contain the revision number of the Power Management Interface Specification. hardwired to 001b. b10..............D2S: D2 Support This bit indicates that DS-1L support "D2" of the power state. It is hardwired to "1". They are
January 14, 1999 -22-
YMF740C
54-55h: Power Management Control / Status
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 PS b0
b[1:0] ..........PS: Power State These bits determine the power state of DS-1L. "0": "1": "2": "3": D0 D1 D2 D3hot (not supported) DS-1L supports the following power states:
When the power state is changed from D3hot to D0, DS-1L resets the PCI Configuration register 00-3Fh. DS-1L transits to D0 Uninitialized state. Though the power state of this register is changed, the power consumption of DS-1L is not changed. support low power, Windows driver controls DS-1L Power Control Register. DS-1L can support the power state of D0, D1, D2 and D3 with ACPI. In this case, set ACPI bit (58-59h: To
ACPI Mode Register) to "1" to disable Capabilities of PCI Bus Power Management.
58-59h: ACPI Mode
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ACPI
b0................ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1L. "0": PCI Bus Power Management is used. (34h) are enabled. "1": ACPI Mode is used. (default) CAP bit and Capabilities Pointer are hardwired "0", and disabled. CAP bit (06-07h: Status Register) and Capabilities Pointer
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YMF740C
2. ISA Compatible Device
DS-1L contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space. Basically, these registers are configured by the BIOS. Also, logical device IDs are assigned to the devices to support Plug and Play. logical IDs. To control the device with the BIOS, the logical device IDs must be defined in the PnP BIOS extended ROM space. The logical IDs are determined by how it is configured. IDs and configuration are as follows. Yamaha defines the following
Logical Device ID YMH0100 YMH0101
Functions used (Block) FM O
(*)
MPU401 O
SB Pro (*) O
Joystick O
* The blocks pertain to the following. FM: SB Pro: Points to the FM synthesizer mapped to AdLibBase (0x0388). Points to the Voice Playback section only. However, both
These devices are independent from each other, and can be Enabled/Disabled individually. AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer. only masks the access. The driver by Yamaha supports only logical device ID, YMH0100. by Microsoft.
Disabling just AdLib
For YMH0101, use the driver provided
DS-1L supports PC/PCI protocol to emulate the DMA of SB Pro on the PCI. the old type of interrupts used by ISA. The PCI-to-ISA bridge needs to support PC/PCI. PCI-to-ISA bridge.
In addition, DS-1L supports
IRQ is directly connected to the IRQ input pins on the
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YMF740C
2-1. FM Synthesizer Block
FM Synthesizer Block is register compatible with YMF289B. However, Power Management register
has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase FMBase FMBase+1 FMBase+2 FMBase+3 (R) (W) (R/W) (W) (R/W) Status Register port Address port for Register Array 0 Data port Address port for Register Array 1 Data port
The default FMBase value is 0x0388. The following shows the FM Synthesizer Block registers.
2-1-1. Status Register FM Synthesizer Status Register (RO):
Address xxh D7 IRQ D6 FT1 D5 FT2 D4 D3 D2 BUSY D1 D0 BUSY
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YMF740C
2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W):
Address 00-01h 02h 03h 04h 08h 20-35h 40-55h 60-75h 80-95h
(*1) (*2) (*3) (*4)
D7
D6
D5
D4
D3
D2
D1
D0
LSI TEST TIMER 1 TIMER 2 RST AM KSL AR SL F-NUM (L) DAM *6 DVB *6 KON RHY CHR BD CHL BLOCK SD TOM FB WS F-NUM (H) TC HH CNT MT1 NTS VIB MT2 EGT KSR TL DR RR MULT ST2 ST1 -
A0-A8h B0-B8h BDh C0-C8h E0-F5h
(*5)
FM Synthesizer Data Register Array 1 (R/W)
Address 00-01h 04h 05h 20-35h 40-55h 60-75h 80-95h
(*1) (*2) (*3) (*4)
D7
D6
D5
D4
D3
D2
D1
D0
LSI TEST AM KSL AR SL F-NUM (L) *6 *6 KON CHR CHL BLOCK FB WS F-NUM (H) CNT VIB EGT KSR TL DR RR CONNECTION SEL * MULT * NEW
A0-A8h B0-B8h C0-C8h E0-F5h
(*5)
*1 : 26h, 27h, 2Eh and 2Fh do not exist. *2 : 46h, 47h, 4Eh and 4Fh do not exist. *3 : 66h, 67h, 6Eh and 6Fh do not exist. *4 : 86h, 87h, 8Eh and 8Fh do not exist. *5 : E6h, E7h, EEh and EFh do not exist. *6 : The bits exist, but do not function.
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YMF740C
2-2. Sound Blaster Pro Block
This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. functions are supported (record functions are not supported). The DMA transfer of this block uses PC/PCI protocol. The following shows the SBBase I/O map of SB Pro. SBBase SBBase SBBase+1h SBBase+2h SBBase+3h SBBase+4h SBBase+5h SBBase+6h SBBase+8h SBBase+8h SBBase+9h SBBase+Ah SBBase+Ch SBBase+Ch SBBase+Eh (R) (W) (R/W) (W) (R/W) (W) (R/W) (W) (R) (W) (R/W) (R) (R) (W) (R) FM Synthesizer Status port FM Synthesizer Address port for Register Array 0 FM Synthesizer Data register FM Synthesizer Address port for Register Array 1 FM Synthesizer Data port SB Mixer Address port SB Mixer Data port SB DSP Reset port FM Synthesizer Status port FM Synthesizer Address port for Register Array 0 FM Synthesizer Data port DSP Read Data port DSP Write-buffer status port DSP Write Command/Data port DSP Read-buffer status port games, it is designed so that every DSP command receives a correct response. Only playback
However, to maintain compatibility for
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YMF740C
2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. SB Pro commands are supported. Both SB and
CMD Support Function
10h 14h 16h 17h 1Ch 1Fh 20h(*1) 24h(*1) 2Ch(*1) 30h 31h 34h 35h 36h(*2) 37h(*2) 38h 40h 48h 74h 75h 76h 77h 7Dh 7Fh 80h 90h 91h 98h(*1) 99h(*1) A0h(*1) A8h(*1) D0h D1h(*3) D3h(*3) D4h D8h DAh E1h o o 8bit direct mode single byte digitized sound output 8bit single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit auto-init DMA mode digitized sound output 8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit direct mode single byte digitized sound input 8bit single-cycle DMA mode digitized sound input 8bit auto-init DMA mode digitized sound input Polling mode MIDI input Interrupt mode MIDI input UART polling mode MIDI I/O UART interrupt mode MIDI I/O UART polling mode MIDI I/O with time stamping UART interrupt mode MIDI I/O with time stamping MIDI output Set digitized sound transfer Time Constant Set DSP block transfer size 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM single-cycle DAM mode digitized sound output 8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte Pause DAC for a duration 8bit high-speed auto-init DMA mode digitized sound output 8bit high-speed single-cycle DMA mode digitized sound output 8bit high-speed auto-init DMA mode digitized sound input 8bit high-speed single-cycle DMA mode digitized sound input Set input mode to mono Set input mode to stereo Pause 8bit DMA mode digitized sound I/O Turn on speaker Turn off speaker Continue 8bit DMA mode digitized sound I/O Get speaker status Exit 8bit auto-init DMA mode digitized sound I/O Get DSP version number
o o o o o o o o o o o o o o o
o o o o o o o o o o o o o o o
Note: (*1) The SB Block responds correctly to the commands for recording and also executes the DMA transfer. 80h is always transferred. (*2) Only output is supported for this command. (*3) This command only changes Speaker Status (D8h). Undocumented commands other than the ones listed above are also supported.
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YMF740C
2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro.
Address 00h 04h 0Ah 0Ch 0Eh 22h 26h 28h 2Eh F0h F1h F8h Voice Volume L Ifilter* Ofilter* "1" "1" "1" "1" "1" "1" "1" "1" SCAN SS DATA SBI b7 b6 b5 b4 Reset Voice Volume R MIC Volume* Input Source* St. SW "1" "1" "1" "1" "1" "1" SE SBPDR Suspend / Resume IRQ Status SB Pro Mixer "1" b3 b2 b1 b0 Remark
Master Volume L MIDI Volume L CD Volume L* Line Volume L* SBPDA -
Master Volume R MIDI Volume R CD Volume R* Line Volume R* SM
The registers marked with * exist, but do not function. DS-1L does not have the circuit that corresponds to the SB Mixer. The conversion for each case is described below. (1) SB Mixer (R) DSP The volume of master, MIDI and Voice, are applied to this case. When the SB register is set, a 14-bit coefficient value is determined from the following conversion table and used as the DSP coefficient. together to obtain the coefficient. These volumes cannot be controlled from PCI Audio block. The attenuation value of Master Volume, MIDI, and voice are summed Therefore, the volume settings on the
SB Mixer are converted to the DSP coefficients of DS-1L or to AC'97 register values.
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YMF740C
(1) Volume for MIDI
MIDI Vol. (26h) 0 0 1 2 3 4 5 6 7
mute
0000h
1
mute
0000h
2
mute
0000h
3
mute
0000h
4
mute
0000h
5
mute
0000h
6
mute
0000h
7
mute
0000h
mute
0000h
-52dB
0029h
-42dB
0082h
-36dB
0103h
-32dB
019Bh
-30dB
0206h
-28dB
028Ch
-26dB
0335h
mute
0000h
-42dB
0082h
-32dB
019Bh
-26dB
0335h
-22dB
0515h
-20dB
0666h
-18dB
080Eh
-16dB
0A24h
Master Vol. (22h)
mute
0000h
-36dB
0103h
-26dB
0335h
-20dB
0666h
-16dB
0A24h
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
mute
0000h
-32dB
019Bh
-22dB
0515h
-16dB
0A24h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
mute
0000h
-30dB
0206h
-20dB
0666h
-14dB
0CC5h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
-4dB
2861h
mute
0000h
-28dB
028Ch
-18dB
080Eh
-12dB
1013h
-8dB
197Ah
-6dB
2013h
-4dB
2861h
-2dB
32D6h
mute
0000h
-26dB
0335h
-16dB
0A24h
-10dB
143Dh
-6dB
2013h
-4dB
2861h
-2dB
32D6h
0dB
3FFFh
The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice
Voice Vol. (04h) 0 0 1 2 3 4 5 6 7
mute
0000h
1
mute
0000h
2
mute
0000h
3
mute
0000h
4
mute
0000h
5
mute
0000h
6
mute
0000h
7
mute
0000h
mute
0000h
-56dB
0019h
-46dB
0052h
-40dB
00A3h
-36dB
0103h
-34dB
0146h
-32dB
019Bh
-30dB
0206h
mute
0000h
-46dB
0052h
-36dB
0103h
-30dB
0206h
-26dB
0335h
-24dB
0409h
-22dB
0515h
-20dB
0666Eh
Master Vol. (22h)
mute
0000h
-40dB
00A3h
-30dB
0206h
-24dB
0409h
-20dB
0666h
-18dB
080Eh
-16dB
0A24h
-14dB
0CC5h
mute
0000h
-36dB
0103h
-26dB
0335h
-20dB
0666h
-16dB
0A24h
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
mute
0000h
-34dB
0146h
-24dB
0409h
-18dB
080Eh
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
mute
0000h
-32dB
019Bh
-22dB
0515h
-16dB
0A24h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
mute
0000h
-30dB
0206h
-20dB
0666h
-14dB
0CC5h
-10dB
143Dh
-8dB
187Ah
-6dB
2013h
-4dB
2861h
The default is Master = 4, Voice = 4 (-16dB). (2) SB Mixer (R) AC'97 The volume of CD, Line and MIC are applied to this case. when these values are changed. the software. AC'97 volume are not updated automatically Thus, the SB Mixer values need to be written to the AC'97 register with
January 14, 1999 -30-
YMF740C
2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. is made up of 218 flip flops. from the SCAN DATA register. These registers are mapped to the SB Mixer space (see SB Mixer Register map). following functions. The registers have the The internal state
To read the state, these states are shifted in order and read 8 bits at a time
F0h: Scan In/ Out Control
Read / Write Default: 00h
b7
SBPDA
b6 -
b5 -
b4 -
b3 SS
b2 SM
b1 SE
b0
SBPDR
b0................SBPDR: Sound Blaster Power Down Request This bit stops the internal state of the Sound Blaster block. "0": Normal "1": Stop b1................SE: Scan Enable This bit Shifts the internal state by 1 bit. b2................SM: Scan Mode This bit sets whether to read or write the state. "0": Write "1": Read b3................SS: Scan Select This bit gives permission to read or write the internal data to the SCAN DATA register. "0": Normal operation (Do not allow read or write). "1": Allow read and write. b7................SBPDA: Sound Blaster Power Down Acknowledgement This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR. This bit is read only. "0": Read/Write not possible "1": Read/ Write possible (default) (default) Setting a "1" followed by a "0" shifts the internal state. (default)
January 14, 1999 -31-
YMF740C
F1h: Scan In/ Out Data
Read / Write Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA
b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state.
F8h: Interrupt Flag Register
Read Only Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 SBI
b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. read port to clearing the interrupt and this bit. This bit is read only. Thus, read the SB DSP
Then, the value of the read port is invalid.
January 14, 1999 -32-
YMF740C
2-3. MPU401
This block is for transmitting and receiving MIDI data. It is compatible with UART mode of "MPU401".
Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving. The following shows the MPUBase I/O map for MPU401. MPUBase MPUBase + 1h MPUBase + 1h
port +0h +1h (W) +1h (R) /DSR /DRR D7
(R/W) (R) (W)
D6
MIDI Data port Status Register port Command Register port
D5 D4 Data Command D3 D2 D1 D0
2-4. Joystick
JSBase
port +0h
(R/W)
D7 JBB2 D6 JBB1 D5 JAB2 D4 JAB1 D3 JBCY D2 JBCX D1 JACY D0 JACX
JACX... JACY... JBCX... JBCY... JAB1... JAB2... JBB1... JBB2...
Joystick A, Coordinate X Joystick A, Coordinate Y Joystick B, Coordinate X Joystick B, Coordinate Y Joystick A, Button 1 Joystick A, Button 2 Joystick B, Button 1 Joystick B, Button 2
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YMF740C
3. DMA Emulation Protocol
The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1L, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block. Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there is a way, that is PC/PCI, proposed from the industry to emulate the ISA DMAC on the PCI bus. DS-1L supports the protocol for transferring SB Pro sound data on the PCI bus.
3-1. PC/PCI
DS-1L provides two signals, PCREQ# and PCGNT# to realize the PC/PCI. The format of the signals is shown below. DS-1L asserts PCREQ# and sets PCREQ# to "HIGH" using the PCICLK corresponding to the DMA channel it is going to use. In addition, DS-1L determines whether the next PCI I/O cycle is its own from the channel information that is encoded in PCGNT#.
0ns PCICLK REQ# GNT# start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 start bit0 bit1 bit2 100ns 200ns 300ns 400ns
PCGNT# is encoded as follows. GNT# Encoding bit2 bit1 bit0 GNT# Bits DMA Channel 0 0 0 0 DMA Channel 1 0 0 1 DMA Channel 2 0 1 0 DMA Channel 3 0 1 1 Reserved 1 0 0 DMA Channel 5 1 0 1 DMA Channel 6 1 1 0 DMA Channel 7 1 1 1 DS-1L supports only 8-bit DMA channels (DMA Channel 0-3).
It also only supports Single DMA transfer.
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YMF740C
4. Interrupt Routing
DS-1L supports two types of interrupts, interrupt signal on the PCI bus (INTA#) and interrupt signal on the ISA bus (IRQ[5,7,9,10,11]). The IRQs on DS-1L are routed as shown below.
INTA#
INTA
PCI Audio
Selector
IMOD=1
IRQ
Selector
IRQ5 IRQ7 IRQ9 IRQ10 IRQ11
IMOD=0
Sound Blaster Pro
ISA IRQ
IMOD=1 IMOD=0
Select Signal SBIRQ[2:0]
IRQ
MPU401
IMOD Select Signal MPUIRQ[2:0]
PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the two protocols. The protocol can be switched using 42-43h (Legacy Audio Control Register) of the PCI Configuration Register.
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YMF740C
5. Hardware Volume Control
The hardware volume control determines the AC'97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used.
Push SW 1k VOLUP# Push SW 1k VOLDW# 1000p 1000p
DS-1L provides a shadow register for the AC'97 master volume. Master Volume, it is always reflected in the shadow register.
When the software accesses the AC'97
The value of the shadow register is incremented by 1.5dB on the rising edge of the signal input to the VOLUP# pin. If it is already set to the maximum value, it does not change. The value set in the shadow
register automatically updates the AC'97 master volume register through the AC-Link. The value of the shadow register is decremented by 1.5dB on the rising edge of the signal input to the VOLDW# pin. If it is already set to the minimum value, it does not change. The value set in the shadow
register automatically updates the AC'97 master volume register through the AC-Link. Also, when both VOLUP#, VOLDW# pins are at LOW level, the MUTE bit of the shadow address is enabled and the Master Volume Mute bit of the AC'97 register is automatically set through the AC-Link. When a The
rising edge is detected on either VOLUP# or VOLDW#, the MUTE bit is reset through the AC-Link. Master Volume is set to the value before the Mute.
If the AC-Link is BUSY (when controlling the register from the AC'97 Control Register), the value in the shadow register is set to AC'97 on the next frame. The AC'97 Control Register is set to BUSY in this case.
When the master volume changes or is muted due to VOLUP#, VOLDW#, an interrupt is generated at the host. The interrupt is used to notify the driver that the Master Volume has been changed from the outside.
January 14, 1999 -36-
YMF740C
ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings
Item Power Supply Voltage 1 (PVDD, VDD5) Power Supply Voltage 2 (VDD3, LVDD) Input Voltage 1 (PVDD, VDD5) Input Voltage 2 (VDD3, LVDD) Operating Ambient Temperature Storage Temperature Note : PVSS=LVSS=VSS=0[V] Symbol VDD5 VDD3 VIN5 VIN3 TOP TSTG Min. -0.5 -0.3 -0.5 -0.3 0 -50 Max. 7.0 4.6 VDD5+0.5 VDD3+0.3 70 125 Unit V V V V C C
2. Recommended Operating Conditions
Item Power Supply Voltage 1 (PVDD, VDD5) Power Supply Voltage 2 (VDD3, LVDD) Operating Ambient Temperature Note : PVSS=LVSS=VSS=0[V] Symbol VDD5 VDD3 TOP Min. 4.75 3.00 0 Typ. 5.00 3.30 25 Max. 5.25 3.60 70 Unit V V C
January 14, 1999 -37-
YMF740C
3. DC Characteristics
Item High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current High Level Output Voltage 1 Low Level Output Voltage 1 High Level Output Voltage 2 Low Level Output Voltage 2 High Level Output Voltage 3 Low Level Output Voltage 3 High Level Output Voltage 4 Low Level Output Voltage 4 Input Pin Capacitance Clock Pin Capacitance IDSEL Pin Capacitance Output Leakage Current Power Supply Current 1 (Normal Operation) Power Supply Current 2 (Power Save) Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 IIL VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 CIN CCLK CIDSEL IOL PVDD+VDD5 VDD3 *9, PVDD+VDD5 *9, VDD3 0.5 6 *1 *1 *2 *2 *3 *3 *4 *4 0< VIN < VDD5 *5, IOH1 = -1mA *5, IOL1 = 3mA *6, IOH2 = -2mA *6, IOL2 = 6mA *7, IOH3 = -4mA *7, IOL3 = 12mA *8, IOH4 = -80A *8, IOL4 = 2mA 5 5 5 -10 VDD5-1.0 0.4 15 15 15 10 60 145 2 10 2.4 0.55 2.4 0.55 -10 2.4 0.55 0.7VDD5 0.2VDD5 10 Condition Min. 2.2 -0.5 2.2 -0.5 2.2 0.8 Typ. Max. VDD5 +0.5 0.8 VDD5 +0.5 0.6 Unit V V V V V V V V A V V V V V V V V pF pF pF A mA mA mA mA
Note : Top = 0~70C, PVDD=5.00.25[V], VDD5=5.00.25[V], VDD3=3.30.3[V], LVDD=3.30.3[V], CL=50 pF *1: Applicable to all PCI Iuput/Output pins and Iunput pins except PCICLK and RST# pin. *2: Applicable to RST# pin. *3: Applicable to CBCLK, CSDI, GP[7:4], RXD and TEST[7:0]# pins. *4: Applicable to XI24 pin. *5: Applicable to AD[31:0], C/BE[3:0]#, PAR, REQ#, PCREQ#, SERIRQ# and TXD pins. *6: Applicable to FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PERR#, SERR#, CRST#, CSYNC and CSDO pins. *7: Applicable to IRQ5, IRQ7, IRQ9, IRQ10, IRQ11 and INTA# pins. *8: Applicable to CMCLK and XO24 pins. *9: DS-1L Power Control Register, DMC=DPLL0=DPLL1=PSN=PSL0=PSL1="1", PCICLK (33MHz) is stopped.
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YMF740C
4. AC Characteristics
4-1. Master Clock Item XI24 Cycle Time XI24 High Time XI24 Low Time (Fig.1) Symbol tXICYC tXIHIGH tXILOW Min. 16 16 Typ. 40.69 Max. 24 24 Unit ns ns ns
Note : Top = 0-70C, PVDD=5.00.25 V, VDD5=5.00.25 V, VDD3=3.30.3 V, LVDD=3.30.3 V
3.5 V
XI24
2.5 V 1.0 V
t XIHIGH
t XILOW
t XICYC
Fig.1: XI24 Master Clock timing 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Symbol tRST tRSTOFF Min. 1 10 50 Typ. Max. Unit ms ms mV/ns
Note : Top = 0-70C, PVDD=5.00.25 V, VDD5=5.00.25 V, VDD3=3.30.3 V, LVDD=3.30.3 V, CL=50 pF
4.75 V
PVDD, VDD5
3.0 V
LVDD, VDD3 t RSTOFF t RST RST#
0.6 V
Fig.2: PCI Reset timing
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YMF740C
4-3. PCI Interface Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK (Fig.3, 4) Symbol tPCYC tPHIGH tPLOW tPVAL tPON tPOFF tPSU tPSU(PTP) tPH (Bused signal) *10 (Point to Point) *11 (Point to Point) (Bused signal) tPVAL(PTP) (Point to Point) Condition Min. 30 11 11 1 2 2 2 7 10 12 0 Typ. Max. 4 11 12 28 Unit ns ns ns V/ns ns ns ns ns ns ns ns ns
Note : Top = 0-70C, PVDD=5.00.25 V, VDD5=5.00.25 V, VDD3=3.30.3 V, LVDD=3.30.3 V, CL=50 pF *10: This characteristic is applicable to REQ# and PCREQ# signal. *11: This characteristic is applicable to GNT# and PCGNT# signal.
2.2 V
PCICLK
1.5 V 0.8 V
t PHIGH t PCYC
t PLOW
Fig.3: PCI Clock timing
PCICLK t PVAL OUTPUT t PON Tri-State OUTPUT t POFF INPUT
Fig.4: PCI Bus Signals timing
1.5 V
1.5 V
t PSU
t PH
1.5 V
January 14, 1999 -40-
YMF740C
4-4. AC'97 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time (Fig.5) Symbol tCMCYC tCMHIGH tCMLOW tCMR tCMF Min. 8 8 Typ. 40.69 4.6 2.1 Max. Unit ns ns ns ns ns
Note : Top = 0-70C, PVDD=5.00.25 V, VDD5=5.00.25 V, VDD3=3.30.3 V, LVDD=3.30.3 V, CL=50 pF
t CMR CMCLK
t CMF
3.5 V 2.5 V 0.4 V
t CMHIGH
t CMLOW
t CMCYC
Fig.5: Master Clock timing for AC'97
January 14, 1999 -41-
YMF740C
4-5. AC-link (Fig.6) Item CBCLK Cycle Time CBCLK High Time CBCLK Low Time CSYNC Cycle Time CSYNC High Time CSYNC Low Time CBCLK to Signal Valid Delay Output Hold Time for CBCLK Input Setup Time to CBCLK Input Hold Time for CBCLK Warm Reset Width
*11: This characteristic is applicable to CSYNC and CSDO signal. *12: This characteristic is applicable to CSDI signal.
Symbol tCBICYC tCBIHIGH tCBILOW tCSYCYC tCSYHIGH tCSYLOW tCVAL tCOH tCISU tCIH *11 *11 *12 *12
Condition
Min. 35 35 0 15 5 -
Typ. 81.4 40.7 40.7 20.8 1.3 19.5 1.3
Max. 45 45 20 -
Unit ns ns ns ns ns ns ns ns ns ns s
Note) Top = 0-70C, PVDD=5.00.25 V, VDD5=5.00.25 V, VDD3=3.30.3 V, LVDD=3.30.3 V, CL=50 pF
t CBICYC
2.2 V
CBCLK t CBIHIGH t CBILOW t CVAL
1.5 V 0.8 V
t COH
2.2 V
t CSYLOW
SYNC t CSYHIGH t CSYCYC t CVAL CSDO
0.8 V
1.5 V 0.8 V
t COH
2.2 V
t CISU CSDI
t CIH
2.2 V 0.8 V
Fig.6: AC-link timing
January 14, 1999 -42-
YMF740C
EXTERNAL DIMENSIONS
YMF740C-V
22.000.40 20.000.30
108 73
109
72
20.000.30
144 37
0 MIN. (STAND OFF)
1
36
1.400.20
1.70MAX.
0.200.10
P-0.50TYP
(1.00)
0-10
LEAD THICKNESS : 0.15+0.10 -0.06
0.500.20
The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. ) should be used as a reference. Plastic body dimensions do not include burr of resin.
January 14, 1999 -43-
22.000.40
YMF740C
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquires to : Semi-conductor Sales Department
- Head Office 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 YAMAHA System Technology. 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791
- Tokyo Office - Osaka Office
- U.S.A. Office
January 14, 1999 -44-

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